STM32CubeIDE Overview
Developing for the Neuro N6 with ST's STM32CubeIDE and the board support package, as an alternative to the Arduino core.
STM32CubeIDE is STMicroelectronics' Eclipse-based development environment for STM32 microcontrollers. Ohm Lab provides a board support package (BSP) for the Neuro N6 that allows the board to be programmed from STM32CubeIDE without the Arduino core. This path suits projects that require direct control of the HAL, a custom RTOS configuration, or integration with existing STM32 code.
Relationship to the Arduino core
The Arduino core and the STM32CubeIDE BSP share the STM32N6 HAL, the CMSIS device headers, the ST Edge AI runtime and the FreeRTOS kernel. The Arduino core adds the Arduino API, the Vision pipeline, TinyUSB, the model build pipeline and the bundled libraries. The BSP exposes the peripherals directly.
Toolchain
STM32CubeIDE bundles its own GCC. Projects for the STM32N657 require STM32CubeIDE 1.16 or later with the STM32N6 device support package. Programming and debugging use an ST-LINK on the board's six-pin debug connector, which carries SWDIO, SWCLK, NRST and the BOOT0 and BOOT1 pins. Debugging and flash programming through STM32CubeProgrammer use the STM32N6 developer boot mode, entered by asserting BOOT1 during reset, with the board's external memory loader. This mode also recovers a board whose FSBL has been erased.
Memory layout
The constraints described in Memory Map apply: the application executes from AXISRAM after the FSBL copies it from external flash, the loaded image must end below 0x34180000, and the image must be signed with STM32CubeProgrammer's signing tool before the FSBL accepts it. A project's linker script is based on the core's STM32N657I0HXQ_LRUN.ld.
Neural networks
ST Edge AI Core generates network code from a .tflite or .onnx model against the board's memory pool description, NeuroN6_MemPool.mpool in the core's system/npu directory. The generated code and the ST Edge AI runtime library are added to the project. The Arduino core's tools/neuron6_model_gen.py shows the command line options used, including the uint8 channel-last input interface the camera pipe requires.
Peripherals
| Peripheral | Notes |
|---|---|
| DCMIPP and CSI-2 | CSI-2 version 1.3 host, two lanes at up to 2.5 Gbit/s. Three pipes: display, JPEG encoder, neural network input. The core's NeuroN6.c contains a working configuration for the OV5640 and VD66GY |
| LTDC | 800x480 panel with two layers, RGB565 output |
| VENC | Hantro hardware encoder, H.264 to 1080p15 and JPEG to 300 Mpixel/s, driven through ST's encoder wrapper layer. 128 KB VENCRAM |
| USB | USB 2.0 OTG high speed with internal PHY. The core uses TinyUSB with a CDC interface and a vendor bulk interface |
| I2C | Two interfaces: one on the Feather header, one on the 40-pin connector for camera control and module sensors |
| SPI1, SPI2 | SPI1 on the 40-pin connector for the Thermal module's video link, and SPI2 on the header |
| MDF1, SAI1 | Microphone and speaker |
| SDMMC1 | The MAYA-W476 wireless module on the -W carriers, over SDIO |
| UART4 | Header RX and TX on PD0 and PD1 |
| ADC1, ADC2 | 12-bit, up to 5 Msps, input range VSSA to VREF+. Header analogue inputs; full scale is 1.8 V |
| MDF1 | Six filters; the microphone uses filter 1 |
| IWDG, WWDG | Independent watchdog, used by the core at 8 s. Window watchdog unused |
| RTC, TAMP | Wake-up timer, 32 backup registers, 8 KB backup SRAM in the VBAT domain |
Several peripherals must be marked secure and privileged in the resource isolation framework (RIFSC) before the secure DMA channels or the GPIO pads will connect to them: the NPU, DMA2D, CSI, DCMIPP, LTDC, ADC12, MDF1 and SAI1. The core's initialisation code shows each case.
Reference documents
The STM32N657 is described in ST datasheet DS14791, reference manual RM0486 and errata sheet ES0620.
Availability
The BSP and an example project are available from Ohm Lab. Documentation for the BSP will be added to this section as it is published.