Memory Map
The STM32N657's on-chip RAM, external PSRAM and external flash as used by the core, the 1.5 MB application limit, and buffer placement.
The STM32N657 has no internal flash. The application is stored in external flash and copied into on-chip RAM by the first stage bootloader (FSBL) at boot. The chip has 4.2 MB of contiguous SRAM plus tightly coupled memories, and the board has 64 MB of external PSRAM and 32 MB of external flash. The core's linker script uses part of each: a 2 MB AXISRAM region for the application and about 30 MB of the PSRAM.
STM32N657 memories
| Memory | Size | Notes |
|---|---|---|
| AXISRAM1 to AXISRAM6 | 4.2 MB contiguous | ECC with single error correction and double error detection. The core's application region is within this |
| AHBSRAM1, AHBSRAM2 | 16 KB each | |
| Data TCM | 128 KB | ECC. Tightly coupled to the Cortex-M55 |
| Instruction TCM | 64 KB | ECC |
| VENCRAM | 128 KB | Video encoder working RAM. Available as system SRAM when the encoder is disabled |
| Backup SRAM | 8 KB | Retained in VBAT mode, alongside 32 backup registers |
| CACHEAXI | A cache on the NPU's AXI path for data in external memory, or configurable as SRAM |
On-chip RAM
| Region | Address | Size | Contents |
|---|---|---|---|
| Application image | 0x34000400 to 0x34180000 | 1.5 MB | Code, read-only data, initialised data |
| FSBL | from 0x34180000 | 512 KB | The bootloader, resident while the application runs |
| Remaining AXISRAM | above the image | .bss, heap, stack, NPU activation buffers, encoder line buffer, display framebuffer |
The application image must end below 0x34180000. The linker script enforces this with an assertion, and boards.txt reports the limit as 1,572,864 bytes to the IDE's size summary.
The encoder line buffer band, about 100 KB at WVGA and 480 KB at 1080p, and the display framebuffer under TRANSPORT_LCD, about 750 KB at WVGA, are placed in AXISRAM by default and fall back to PSRAM when they do not fit. cfg.band_loc and cfg.framebuf_loc force either placement.
External PSRAM
The board carries 64 MB of OctoSPI PSRAM (AP Memory APS51208N) mapped from 0x70000000. The STM32N6 XSPI runs in memory-mapped mode at up to 200 MHz and includes a cipher engine for on-the-fly encryption of external memory, which the core does not use. The core's linker script currently defines a region of about 30 MB, of which about 28 MB forms a pool available to the application. The .ext_psram section places static buffers in it:
static uint8_t g_frame[256 * 256 * 3] __attribute__((aligned(32), section(".ext_psram")));Contents of the pool at run time:
| User | Size |
|---|---|
| JPEG output buffers | About 1 MB at VGA, up to 2.5 MB at 5 MP |
| Display overlay layer | 768 KB, always in PSRAM |
| Display camera layer, second buffer | 768 KB at WVGA, for double buffering |
| NPU activations | Model dependent, from the memory pool description |
Sketch buffers in .ext_psram | As declared |
| Event ring, motion gate | From the pool, allocated after Vision.begin() |
n6_psram_alloc() allocates from the pool at run time. Vision.begin() resets the pool, so allocations that must persist are made after it.
Reads from PSRAM are uncached and slower than on-chip RAM. Buffers that are read repeatedly by the CPU, such as an image being processed, are the main cost. DMA destinations in PSRAM must be aligned to 16 bytes; aligned(32) is used.
External flash
32 MB of OctoSPI flash (Macronix MX25UM25645G), memory mapped from 0x90000000.
| Region | Address | Contents |
|---|---|---|
| FSBL | 0x90000000 to 0x90100000 | The bootloader. Protected; not to be overwritten |
| Application | 0x90100000 | The signed _Trusted.bin, copied to RAM at boot. Two slots for A/B updates |
| Model weights pool | 0x90300000 to 0x91D80000 | 26.5 MB. Models pack in pragma order at 64 KB alignment |
| WiFi module firmware | 0x91E00000 | The IW610 firmware |
| Asset store, calibration | Persistent data written by the bootloader |
The application never writes flash. Uploads, model weights, over-the-air updates, camera calibration and assets are all written by the bootloader after a reset. A board whose FSBL has been corrupted or erased is recovered through the STM32N6 developer boot mode, entered by asserting BOOT1 on the debug connector, with STM32CubeProgrammer and the board's external memory loader. Mapped flash reads from the application are wrong about 0.9% of the time on this part; the asset store CRC-checks and retries reads internally.
Cache and coherence
The data cache is enabled. DMA buffers that must be coherent are placed in a non-cacheable AXISRAM window defined by the MPU, or are cache-cleaned and invalidated around transfers. The encoder line buffer lives in the non-cacheable window. The microphone invalidates its receive buffer; the speaker cleans its transmit buffer.
Size reporting
The build's size step prints the section table and the IDE computes its summary from it. Minimal build output shows RAM and image use; verbose output shows the full breakdown. -Os (Tools > Optimize > Smallest) reduces the image for sketches near the limit. The link uses newlib-nano with float printf support forced in, because the NPU runtime formats floats.
Diagnostic sketches
PsramSizeProbe, PsramStress, PsramRetention and PsramDecay in extras/bench test the external memory for aliasing, faults, retention across a power cycle and long-soak retention. FlashReadRepeatability measures the mapped-read error rate.